// Peripheral: DCMI_Periph  DCMI.
// Instances:
//  DCMI  mmap.DCMI_BASE
// Registers:
//  0x00 32  CR      Control register 1.
//  0x04 32  SR      Status register.
//  0x08 32  RISR    Raw interrupt status register.
//  0x0C 32  IER     Interrupt enable register.
//  0x10 32  MISR    Masked interrupt status register.
//  0x14 32  ICR     Interrupt clear register.
//  0x18 32  ESCR    Embedded synchronization code register.
//  0x1C 32  ESUR    Embedded synchronization unmask register.
//  0x20 32  CWSTRTR Crop window start.
//  0x24 32  CWSIZER Crop window size.
//  0x28 32  DR      Data register.
// Import:
//  stm32/o/f746xx/mmap
package dcmi

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	CAPTURE CR = 0x01 << 0  //+
	CM      CR = 0x01 << 1  //+
	CROP    CR = 0x01 << 2  //+
	JPEG    CR = 0x01 << 3  //+
	ESS     CR = 0x01 << 4  //+
	PCKPOL  CR = 0x01 << 5  //+
	HSPOL   CR = 0x01 << 6  //+
	VSPOL   CR = 0x01 << 7  //+
	FCRC_0  CR = 0x01 << 8  //+
	FCRC_1  CR = 0x01 << 9  //+
	EDM_0   CR = 0x01 << 10 //+
	EDM_1   CR = 0x01 << 11 //+
	CRE     CR = 0x01 << 12 //+
	ENABLE  CR = 0x01 << 14 //+
	BSM     CR = 0x03 << 16 //+
	BSM_0   CR = 0x01 << 16
	BSM_1   CR = 0x02 << 16
	OEBS    CR = 0x01 << 18 //+
	LSM     CR = 0x01 << 19 //+
	OELS    CR = 0x01 << 20 //+
)

const (
	CAPTUREn = 0
	CMn      = 1
	CROPn    = 2
	JPEGn    = 3
	ESSn     = 4
	PCKPOLn  = 5
	HSPOLn   = 6
	VSPOLn   = 7
	FCRC_0n  = 8
	FCRC_1n  = 9
	EDM_0n   = 10
	EDM_1n   = 11
	CREn     = 12
	ENABLEn  = 14
	BSMn     = 16
	OEBSn    = 18
	LSMn     = 19
	OELSn    = 20
)

const (
	HSYNC SR = 0x01 << 0 //+
	VSYNC SR = 0x01 << 1 //+
	FNE   SR = 0x01 << 2 //+
)

const (
	HSYNCn = 0
	VSYNCn = 1
	FNEn   = 2
)

const (
	FRAME_IE IER = 0x01 << 0 //+
	OVR_IE   IER = 0x01 << 1 //+
	ERR_IE   IER = 0x01 << 2 //+
	VSYNC_IE IER = 0x01 << 3 //+
	LINE_IE  IER = 0x01 << 4 //+
)

const (
	FRAME_IEn = 0
	OVR_IEn   = 1
	ERR_IEn   = 2
	VSYNC_IEn = 3
	LINE_IEn  = 4
)

const (
	FRAME_ISC ICR = 0x01 << 0 //+
	OVR_ISC   ICR = 0x01 << 1 //+
	ERR_ISC   ICR = 0x01 << 2 //+
	VSYNC_ISC ICR = 0x01 << 3 //+
	LINE_ISC  ICR = 0x01 << 4 //+
)

const (
	FRAME_ISCn = 0
	OVR_ISCn   = 1
	ERR_ISCn   = 2
	VSYNC_ISCn = 3
	LINE_ISCn  = 4
)

const (
	FSC ESCR = 0xFF << 0  //+
	LSC ESCR = 0xFF << 8  //+
	LEC ESCR = 0xFF << 16 //+
	FEC ESCR = 0xFF << 24 //+
)

const (
	FSCn = 0
	LSCn = 8
	LECn = 16
	FECn = 24
)

const (
	FSU ESUR = 0xFF << 0  //+
	LSU ESUR = 0xFF << 8  //+
	LEU ESUR = 0xFF << 16 //+
	FEU ESUR = 0xFF << 24 //+
)

const (
	FSUn = 0
	LSUn = 8
	LEUn = 16
	FEUn = 24
)

const (
	BYTE0 DR = 0xFF << 0  //+
	BYTE1 DR = 0xFF << 8  //+
	BYTE2 DR = 0xFF << 16 //+
	BYTE3 DR = 0xFF << 24 //+
)

const (
	BYTE0n = 0
	BYTE1n = 8
	BYTE2n = 16
	BYTE3n = 24
)
